Inverters (e.g., a phase leg inverter) are utilized for a variety of electrical applications. FIG. 1, for example, is a diagram of a prior art phase leg inverter 100 having a voltage rail 108 coupled to a ground rail 118. Voltage rail 108 generally includes a switch 110 coupled in parallel with a diode 115 and, ground rail typically includes a switch 120 coupled in parallel with a diode 125, wherein diodes 115 and 125 are anti-parallel with respect to one another. Moreover, voltage rail 108 and ground rail 118 include a node 130 disposed between them such that positive current flows from ground through diode 125 (or through switch 120 when ON), and negative current flows to a voltage source through diode 115 (or through switch 110 when ON) when switches 110 and 120 are simultaneously OFF.
In typical phase leg inverters, a blanking period is often needed to prevent a shoot-through failure of the phase leg caused by a simultaneously ON condition in switches 110 and 120 when switching ON either switch 110 or 120. This blanking period consists of a short duration of time where switches 110 and 120 are both OFF at the same time, and is commonly referred to as a “dead-time” period.
During dead-time periods, the output voltage of inverter 100 is determined by the polarity of the current flowing through the phase leg (i.e., as the current flows through one of diodes 115 or 125 to voltage rail 108 or ground 118, respectively). For example, current flowing through diode 125 (i.e., positive current (ia>0)) produces zero voltage at node 130 with respect to ground rail 118. Similarly, current flowing through diode 115 (i.e., negative current (ia<0)) produces a positive voltage at node 130 with respect to ground rail 118.
FIG. 2 is a timing diagram 200 illustrating a representation of a conventional method of inserting a dead-time period to prevent a shoot-through failure in inverter 100 for a non-inverted carrier signal. In FIG. 2, a line 240 represents a phase α modulating signal and a line 245 represents a non-inverted carrier signal. In an ideal switching pulse represented by a line 210 (“ideal pulse 210”), when carrier signal 245 is below phase α modulating function 240, switch 110 is switched ON, and is switched OFF when carrier signal 245 is above phase α modulating function 240. Similarly, in an ideal switching pulse represented by a line 220 (“ideal pulse 220”), when carrier signal 245 is above phase α modulating function 240, switch 120 is switched ON, and is switched OFF when carrier signal 245 is below phase α modulating function 240. Since it is desirable that switches 110 and 120 not be ON at the same time, a common technique provides a period of time where switches 110 and 120 are both OFF prior to switching ON either switch 110 or 120.
Lines 110′ and 120′ each represent a typical switching pulse (“pulse 110” and “pulse 120”) including a dead-time period for switches 110 and 120, respectively. As illustrated in FIG. 2, at time t1 (i.e., when carrier signal 245 changes from being above phase α modulating function 240 to being below phase α modulating function 240), switch 120 is switched OFF, as represented by the falling edge of pulse 120′ (which is equally represented in ideal pulse 220). Also at time t1, switch 110 should ideally be switched ON (as illustrated in ideal pulse 210); however, to compensate for the potential harm of both switches 110 and 120 being simultaneously ON, the switching ON of switch 110 is delayed a pre-determined amount of time. This delay is represented by the rising edge of pulse 110′ occurring at a time after time t1, which causes a dead-time period represented by box 260 (“dead-time 260”). Moreover, dead-time 260 causes switch 110 to be ON a shorter period of time than the ideal period of time represented by ideal pulse 210. This shorter period of ON time of switch 110 results in inverter 100 outputting an amount of voltage that deviates from the amount of output voltage inverter 100 would otherwise output if dead-time period 260 was not inserted.
Likewise, at time t2 (i.e., when carrier signal 245 changes from being below phase α modulating function 240 to being above phase α modulating function 240), switch 110 is switched OFF, as represented by the falling edge of pulse 110′ (which is equally represented in ideal pulse 210). Also at time t2, switch 120 should ideally be switched ON (as illustrated in ideal pulse 220); however, to compensate for the potential harm of both switches 110 and 120 being simultaneously ON, the switching ON of switch 120 is delayed a pre-determined amount of time. This delay is represented by the rising edge of pulse 120′ occurring at a time after time t2, which causes a dead-time period represented by box 265 (“dead-time 265”). Moreover, dead-time 265 causes switch 120 to be ON a shorter period of time than the ideal period of time represented by ideal pulse 220. This shorter period of time results in inverter 100 outputting an amount of voltage that deviates from the amount of output voltage inverter 100 would otherwise output if dead-time period 265 was not inserted.
Notably, the current at node 130 determines the voltage output by inverter 100 when switches 110 and 120 are simultaneously OFF. Specifically, when the current at node 130 is negative, inverter 100 outputs a positive voltage. Moreover, when the current at node 130 is positive, the output of inverter 100 zero, with respect to ground rail.
FIG. 3 is a timing diagram 300 illustrating a representation of a known method of inserting a dead-time period to prevent a shoot-through failure of inverter 100 caused by a simultaneously ON condition for inverted carrier signals. In FIG. 3, lines 310 and 320 each represent an ideal switching pulse (“ideal pulse 310” and “ideal pulse 320”) for switches 110 and 120, respectively. Similar to the discussion above, switches 110 and 120 should not be ON at the same time, and to prevent such an event from occurring, a period of time where switches 110 and 120 are both OFF prior to switching either switch 110 or 120 ON is inserted.
As illustrated in FIG. 3, at time t1 (i.e., when an inverted carrier signal 345 (“carrier signal 345”) changes from being below phase α modulating function 240 to being above phase α modulating function 240), switch 110 is switched OFF, as represented by the falling edge of pulse 110′ (which is also equally represented in ideal pulse 310). At time t1, switch 120 should ideally be switched ON (as illustrated in ideal pulse 320); however, to compensate for the potential harm of both switches 110 and 120 being simultaneously ON, the operation of turning ON switch 120 is delayed a pre-determined amount of time. This delay is represented by the rising edge of pulse 120′ occurring at a time after time t1, which causes a dead-time period represented by box 365 (“dead-time 365”). Moreover, dead-time 365 causes switch 120 to be ON a shorter period of time than the ideal period of time represented by ideal pulse 320. This shorter period of time results in inverter 100 outputting an amount of voltage that deviates from the amount of output voltage inverter 100 would otherwise output if dead-time period 365 was not inserted.
Likewise, at time t2 (i.e., when carrier signal 345 changes from being above phase α modulating function 240 to being below phase α modulating function 240), switch 120 is switched OFF, as represented by the falling edge of pulse 120′ (which is also equally represented in ideal pulse 320). At time t2, switch 110 should ideally be switched ON (as illustrated in ideal pulse 310); however, to compensate for the potential harm of both switches 110 and 120 being simultaneously ON, the switching ON of switch 110 is delayed a pre-determined amount of time. This delay is represented by the rising edge of pulse 110′ occurring at a time after time t2, which causes a dead-time period represented by box 360 (“dead-time 360”). Moreover, dead-time 360 causes switch 110 to be ON a shorter period of time than the ideal period of time represented by ideal pulse 310. This shorter period of time results in inverter 100 outputting an amount of voltage that deviates from the amount of output voltage inverter 100 would otherwise output if dead-time period 360 was not inserted.
Similar to the non-inverted signal discussed with reference to FIG. 2, the current at node 130 determines the voltage output by inverter 100 when switches 110 and 120 are simultaneously OFF. Specifically, when the current at node 130 is negative, inverter 100 outputs a positive voltage. Moreover, when the current at node 130 is positive, the output voltage of inverter 100 is zero, with respect to ground rail.
FIG. 4 is a timing diagram 400 illustrating a representation of the voltage output of inverter 100 for non-inverted carrier signal 245 when method 200 is utilized to prevent a shoot-through failure. As illustrated, an ideal area 410 represents the voltage output (in volt•seconds) for an ideal inverter (i.e., an inverter not needing dead-time periods to prevent shoot-through failures), wherein the ideal inverter would begin outputting voltage when carrier signal 245 passes below phase α modulating function 240, and stop outputting voltage when carrier signal 245 passes above phase α modulating function 240.
As illustrated for inverter 100 (i.e., a non-ideal inverter) in FIG. 4, an area 110NP represents the amount of voltage output of inverter 100 when dead-time periods 260 and 265 are inserted to prevent a shoot-through failure in inverter 100 with positive current at node 130. Similarly, an area 110NN represents another area of voltage output of inverter 100 when dead-time periods 260 and 265 are inserted to prevent a shoot-through failure in inverter 100 with negative current at node 130. Comparing area 110NP to ideal area 410 and area 110NN to ideal area 410, it is evident that when inverter 100 implements the dead-time insertion method represented by timing diagram 200, the amount of volt•seconds inverter 100 outputs is different from the ideal amount.
FIG. 5 is a timing diagram 500 illustrating the voltage output of inverter 100 for inverted carrier signal 345 when method 300 is utilized to prevent a shoot-through failure. As illustrated, ideal areas 510A and 510B represent the voltage output (in volt•seconds) for an ideal inverter, wherein the ideal inverter would begin outputting voltage when carrier signal 345 passes below phase α modulating function 240, and stop outputting voltage when carrier signal 345 passes above phase α modulating function 240.
As illustrated in FIG. 5, areas 110IPA and 110IPB represent the amount of voltage output of inverter 100 when dead-time periods 360 and 365 are inserted to prevent a shoot-through failure for positive current at node 130. Similarly, areas 110INA and 110INB represent the amount of voltage output of inverter 100 when dead-time periods 360 and 365 are inserted to prevent a shoot-through failure for negative current at node 130. Comparing the sum of areas 110IPA and 110IPB to the sum of ideal areas 510A and 510B, and the sum areas 110INA and 110INB to the sum of areas 510A and 510B, it is evident that when inverter 100 implements the dead-time insertion method represented by timing diagram 300, the amount of volt•seconds inverter 100 outputs is different from the ideal amount.
Notably, for some applications of inverter 100 it is advantageous to at least occasionally invert the carrier pulse sequence, which also desirably includes periods of dead-time to prevent shoot-through failures. However, switching between non-inverted and inverted carrier signals, even occasionally, may present another problem since the transition between pulse sequence types may require an additional period of dead-time per cycle, in addition to the already one dead-time period per cycle methods represented by timing diagrams 200 and 300. Specifically, when the carrier pulse sequence changes from a non-inverted signal to an inverted signal or changes from an inverted signal to a non-inverted signal, an additional dead-time period should be inserted into the cycle to prevent a shoot-though failure.
With reference to FIG. 6, a timing diagram 600 illustrates a representation of a current method of inserting a dead-time period to prevent a shoot-through failure in inverter 100 when the carrier signal switches between carrier signal 245 and carrier signal 345. In FIG. 6, a line 610p represents a typical switching pulse including dead-time periods for switch 110. As discussed above with reference to FIG. 2, switch 110 includes one dead-time period 260 per cycle for non-inverted carrier signal 245. Accordingly, each of cycles 1 and 3 includes one dead-time period 260 (which results in inverter 100 outputting a deviated amount of volt•seconds (see FIG. 4, area 110NP compared to ideal area 410)). Moreover, as discussed above with reference to FIG. 3, switch 110 includes one dead-time period 360 per cycle for inverted carrier signal 345. Accordingly, cycle 2 includes one dead-time period 360 (which results in inverter 100 outputting a deviated amount of volt•seconds (see FIG. 5, area 110IPB compared to ideal area 510B)).
As illustrated, however, when the carrier signal switches from carrier signal 245 to carrier signal 345 (i.e., transitions from cycle 1 to cycle 2), an additional dead-time period 660 is needed in cycle 2 to prevent a shoot-through failure since there is an additional transition of carrier signal 245 from being above phase α modulating function 240 to being below phase α modulating function 240 when the carrier signal changes from a non-inverted signal to an inverted signal. Dead-time period 660 results in a further deviated voltage output for inverter 100 in cycle 2 in addition to the deviated amount illustrated by area 110NP in FIG. 4.
Similarly, a line 610N represents the ON/OFF switching action of switch 120. As discussed above with reference to FIG. 2, switch 120 includes one dead-time period 265 per cycle for non-inverted carrier signal 245. Accordingly, each of cycles 1 and 3 includes one dead-time period 265 (which results in inverter 100 outputting a deviated amount of volt•seconds (see FIG. 4, area 110NN compared to ideal area 410)). Moreover, as discussed above with reference to FIG. 3, switch 120 includes one dead-time period 365 per cycle for inverted carrier signal 345. This results in inverter 100 outputting a deviated amount of volt•seconds (see FIG. 5, area 110INA compared to ideal area 510A).
As illustrated, however, when the carrier signal switches from carrier signal 345 to carrier signal 245 (i.e., transitions from cycle 2 to cycle 3), an additional dead-time period 665 is needed in cycle 3 to prevent a shoot-through failure since there is an additional transition of carrier signal 345 from being below phase α modulating function 240 to being above phase α modulating function 240 when the carrier signal changes from an inverted signal to a non-inverted signal 245. Dead-time period 665 results in a further deviated voltage output for inverter 100 in cycle 3 in addition to the deviated amount illustrated by area 110NN in FIG. 4.
Therefore, utilizing dead-time periods to prevent shoot-through failures in inverter 100 results in a deviation from the desired amount of volt•seconds output by inverter 100. In addition, the insertion of dead-time periods occurs regardless of whether the carrier signal is non-inverted or inverted, or the polarity of the current at node 130. Moreover, when the carrier signal transitions from a non-inverted to an inverted carrier signal or from an inverted to a non-inverted carrier signal, an additional dead-time period is needed to prevent shoot-through failures, which results in additional voltage output deviation for inverter 100. Accordingly, for inverter 100 to output a desired amount of output voltage, it is desirable to provide a compensation method that accounts for and corrects the voltage deviations resulting from the insertion of dead-time periods for both non-inverted and inverted carrier signals, as well as for situations where the carrier signal transitions between non-inverted and inverted signals. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.